1. Field of the Invention
The present invention relates to a CPU cache architecture and, more particularly, to a lightweight architecture for aliased memory operations, the architecture being able to further improve the performance of a CPU by supporting aliased memory operations in terms of hardware only with minimum modifications of an architecture by reducing address conversion operations, which are executed at tens of to hundreds of cycles in the CPU in aliased memory operations, into one or two cycles by adding a hardware alias table (HAT).
2. Description of the Related Art
A microprocessor is also called a processor, a core, and a central processing unit (CPU). A cache of a CPU is physically a high-speed memory structure disposed between a main memory and a CPU in a computer.
The object of the cache in a CPU is to reduce a data access time and an effective memory access time for executing commands. Such a cache keeps commands that are likely to be accessed and redundant copies of data in a memory physically close to a CPU, thereby using space and time locality. In particular, writing and reading on a cache would be several-times faster than writing and reading on external memories (e.g. external DRAM, SRAM, flash memory and/or a storage such as a tape or a disk, which will be generally referred to as “external memories).
An example of using a cache in a CPU can be seen from Korean Patent Application Publication No. 2013-0109247 (published on 7 Oct., 2013). According to this document, when a requested data or command does not exist in a cache, a cache miss is generated and the data or command is transmitted from an external memory. That is, it can be seen that an effective memory access time of a single level cache is “cache access time”×“cache hit rate”+“cache miss penalty”×cache miss rate”. If a multi-level cache is used, the effective memory access time is further reduced. In other words, as the level of caches increases, the size gradually increases and they are related to gradually increasing cache “miss” penalty. Accordingly, common microprocessors generally require a level 1 cache access time of 10-30 CPU clock cycles, a level 2 cache access time of 10-80 clock cycles, and an off-chip access time of 80-200 clock cycles.
An aliased memory operation is used to safely perform operations without damage to original data by creating a copy when accessing a specific space in a memory.
The aliased memory operation has been performed in a software type because there has been no hardware support from CPU architectures in the related art, in which copies are created and recorded in a software alias table (SAT), which is a table using a memory address before being changed as a key. When it is requested to write an address on an aliased memory, a CPU performs a series of operations for converting the requested address, which is called hashing, whereby it finds out the address where a copy is supposed to be kept in an SAT and keeps information to be recorded at the address. When it is requested to read an aliased memory, a CPU finds out the memory address where a copy is kept through hashing, and when a copy of the value of the requested address actually exists at the position in the SAT, the CPU reads the value of the copy, but when there is no copy, the CPU reads the original value of the address before it is changed.
Since the SAT that is used for aliased memory operations is kept in a memory, it is possible to quickly access it through a cache, but it is required to covert a requested address into the address in the SAT through hashing in every operation, and the conversion through hashing is performed at tens of to hundreds of cycles in the CPU, so it takes a long time to access copies in the SAT and there is a limit in improving the ability for aliased memory operations.